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Disambiguation of "Hsieh, Ping-Hsuan"

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A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.

, , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 50 (8): 1917-1931 (2015)

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Shuo-Chun Hsieh

Shelley Ching-yu Hsieh

Ju-Lan Hsieh

Ping-Ping Tsai

Chih-sheng Hsieh

 

Other publications of authors with the same name

Introduction to the Special Section on High-Speed Wireline and Optical Communication Circuits and Systems., , and . IEEE Open J. Circuits Syst., (2021)IoT: Source of test challenges., , , , , , , , , and 4 other author(s). ETS, page 1-10. IEEE, (2016)Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages., , and . IEEE J. Solid State Circuits, 44 (9): 2488-2495 (2009)Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)., , , , and . IEEE J. Solid State Circuits, 56 (1): 3-6 (2021)Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs., and . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (3): 237-241 (2007)A 13.56-MHz Wireless Power Transfer Transmitter with Impedance Compression Network for Biomedical Applications., and . ISCAS, page 1-5. IEEE, (2020)28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS., , , , , and . ISSCC, page 474-475. IEEE, (2014)7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS., , , , , and . ISSCC, page 136-138. IEEE, (2024)A 100-MHz radio-frequency energy harvester for passively powered devices., and . ECCTD, page 1-4. IEEE, (2015)Minimizing the supply sensitivity of CMOS ring oscillator by jointly biasing the supply and control voltage., , and . CICC, page 531-534. IEEE, (2008)