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Disambiguation of "Stuecheli, Jeffrey"

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Advanced features in IBM POWER8 systems.

, , , , , , , , , , , , , , , and . IBM J. Res. Dev., (2015)

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Jeffrey Johnson

Jeffrey Gaynor

Jeffrey Donahue

jeffrey Wimmer

Jeffrey Windisch

 

Other publications of authors with the same name

The cache and memory subsystems of the IBM POWER8 processor., , , , , , , , , and . IBM J. Res. Dev., (2015)Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era., , and . MICRO, page 24-35. ACM, (2011)IBM POWER9 memory architectures for optimized systems., , , , , , and . IBM J. Res. Dev., 62 (4/5): 3:1-3:13 (2018)A bandwidth-aware memory-subsystem resource management using non-invasive resource profilers for large CMP systems., , , and . HPCA, page 1-11. IEEE Computer Society, (2010)The virtual write queue: coordinating DRAM and last-level cache policies., , , , and . ISCA, page 72-82. ACM, (2010)MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level Caches., , , and . PACT, page 205-206. IEEE Computer Society, (2011)CAPI: A Coherent Accelerator Processor Interface., , , and . IBM J. Res. Dev., (2015)IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI., , , , , , , and . IBM J. Res. Dev., 62 (4/5): 8:1-8:8 (2018)Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue., , , , and . IEEE Micro, 31 (1): 90-98 (2011)Bank-aware Dynamic Cache Partitioning for Multicore Architectures., , and . ICPP, page 18-25. IEEE Computer Society, (2009)