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Disambiguation of "Leenstra, Jens"

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Advanced features in IBM POWER8 systems.

, , , , , , , , , , , , , , , and . IBM J. Res. Dev., (2015)

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Bernd Jenssen

Constanze Jenschke

Meiko Jensen

Fritz Jensen

Gerd Jensch

 

Other publications of authors with the same name

Scan chain clustering for test power reduction., , , , , and . DAC, page 828-833. ACM, (2008)BIST Power Reduction Using Scan-Chain Disable in the Cell Processor., , , and . ITC, page 1-8. IEEE Computer Society, (2006)Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI., , , , , , , , , and 19 other author(s). IBM J. Res. Dev., 51 (5): 529-544 (2007)Issues in the test of artificial neural networks., , , and . ICCD, page 487-490. IEEE, (1989)Hierarchical test assembly for macro based VLSI design., and . ITC, page 520-529. IEEE Computer Society, (1990)Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process., , and . J. Low Power Electron., 3 (1): 54-59 (2007)A 1.8-GHz instruction window buffer for an out-of-order microprocessor core., , , , , and . IEEE J. Solid State Circuits, 36 (11): 1628-1635 (2001)On structured gate forest VLSI design., , , , and . Microprocessing and Microprogramming, 27 (1-5): 785-792 (1989)Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors., , , , , , and . DAC, page 89-94. ACM Press, (1997)IBM POWER8 processor core microarchitecture., , , , , , , , , and 10 other author(s). IBM J. Res. Dev., (2015)