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Disambiguation of "Cheng, Hsiang-Yun"

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EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors.

, , , , , , , and . ACM Trans. Archit. Code Optim., 12 (2): 17:1-17:22 (2015)

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Yun-Chien Cheng

Hsiang Kuang

Cheng-Yung Cheng

Bettina Yunis

Jong-Mo Yun

 

Other publications of authors with the same name

Memory Latency Reduction via Thread Throttling., , , and . MICRO, page 53-64. IEEE Computer Society, (2010)Retinex Based on Weaken Factor with Truncated AGCWD for Backlight Image Enhancement., , , , , and . ICCE, page 1-5. IEEE, (2022)LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches., , , , , , and . ISCA, page 103-114. IEEE Computer Society, (2016)The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper., , , , , , , , , and 2 other author(s). ICCAD, page 1-6. ACM, (2019)EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors., , , , , , , and . ISLPED, page 303-306. ACM, (2014)Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference., , and . ACM Trans. Design Autom. Electr. Syst., 21 (1): 7:1-7:26 (2015)EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors., , , , , , , and . ACM Trans. Archit. Code Optim., 12 (2): 17:1-17:22 (2015)This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator., , , , , and . ASP-DAC, page 702-707. IEEE, (2022)RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment., , , and . DATE, page 400-405. IEEE, (2022)Tensor Movement Orchestration in Multi-GPU Training Systems., , , and . HPCA, page 1140-1152. IEEE, (2023)