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A Clock-Less Jitter Spectral Analysis Technique., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (8): 2263-2272 (2008)A new sigma-delta modulator architecture for testing using digital stimulus., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 51-I (1): 206-213 (2004)An FPGA-based re-configurable functional tester for memory chips., , , and . Asian Test Symposium, page 51-57. IEEE Computer Society, (2000)Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus., and . VTS, page 123-128. IEEE Computer Society, (2002)Delta-sigma modulator based mixed-signal BIST architecture for SoC., , and . ASP-DAC, page 669-674. ACM, (2003)A Scalable On-Chip Jitter Extraction Technique., , , and . VTS, page 267-272. IEEE Computer Society, (2004)Bit-Error-Rate Estimation for High-Speed Serial Links., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (12): 2616-2627 (2006)BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics., , and . ITC, page 1138-1147. IEEE Computer Society, (2004)A BIST Scheme for On-Chip ADC and DAC Testing., , and . DATE, page 216-220. IEEE Computer Society / ACM, (2000)Random Jitter Extraction Technique in a Multi-Gigahertz Signal., , , and . DATE, page 286-291. IEEE Computer Society, (2004)