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Yield Improvement, Fault-Tolerance to the Rescue?.

, , , , , и . IOLTS, стр. 165-166. IEEE Computer Society, (2008)

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Elena Sergeyev

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Dieter Sergel

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Random Adjacent Sequences: An Efficient Solution for Logic BIST., , , , и . VLSI-SOC, том 218 из IFIP Conference Proceedings, стр. 413-424. Kluwer, (2001)A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction., , , , , , , , и . European Test Symposium, стр. 81-86. IEEE Computer Society, (2010)Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes., , , , , , и . European Test Symposium, стр. 132-137. IEEE Computer Society, (2010)Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles., , , , и . VLSI-SoC, том 240 из IFIP, стр. 267-281. Springer, (2005)On hardware generation of random single input change test sequences., , , , и . ETW, стр. 117-123. IEEE Computer Society, (2001)Intra-Cell Defects Diagnosis., , , , , , и . J. Electron. Test., 30 (5): 541-555 (2014)A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction., , , , , , и . J. Electron. Test., 24 (4): 353-364 (2008)A new test pattern generation method for delay fault testing., , , , и . VTS, стр. 296-301. IEEE Computer Society, (1996)Defect Analysis for Delay-Fault BIST in FPGAs., , , и . IOLTS, стр. 124-128. IEEE Computer Society, (2003)Comprehensive bridging fault diagnosis based on the SLAT paradigm., , , , , , , и . DDECS, стр. 264-269. IEEE Computer Society, (2009)