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Disambiguation of "Meinerzhagen, Pascal"

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A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.

, , , , , and . NEWCAS, page 1-4. IEEE, (2013)

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Bernd Meinerzhagen

Bernd Meinerzhagen

Bernd Meinerzhagen

Bernd Meinerzhagen

Wilhelm Meinerzhagen

 

Other publications of authors with the same name

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (2): 222-232 (2016)Replica bit-line technique for embedded multilevel gain-cell DRAM., , and . NEWCAS, page 77-80. IEEE, (2012)ISLPED 2023: International Symposium on Low-Power Electronics and Design., , , and . IEEE Des. Test, 41 (1): 93-94 (February 2024)A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write., , , , , and . NEWCAS, page 1-4. IEEE, (2013)An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop., , , , , , and . ESSCIRC, page 1-4. IEEE, (2019)Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation., , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (12): 1362-1366 (2017)A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (8): 2622-2633 (2016)A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (6): 806-817 (2016)Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS., , , , and . ESSCIRC, page 197-200. IEEE, (2013)