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bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.

P. Meinerzhagen, O. Andersson, B. Mohammadi, S. Sherazi, A. Burg, and J. Rodrigues. ESSCIRC, page 321-324. IEEE, (2012)

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Andreas Burg

Peter Burg

Other publications of authors with the same name

Dynamic SCL Decoder With Path-Flipping for 5G Polar Codes.Y. Shen, A. Balatsoukas-Stimming, X. You, C. Zhang, and A. Burg. IEEE Wirel. Commun. Lett., 11 (2): 391-395 (2022)A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code.P. Giard, A. Balatsoukas-Stimming, T. Müller, A. Burg, C. Thibeault, and W. Gross. CoRR, (2017)Random sampling ADC for sparse spectrum sensing.P. Maechler, N. Felber, and A. Burg. EUSIPCO, page 1200-1204. IEEE, (2011)A multi-Gbps unrolled hardware list decoder for a systematic polar code.P. Giard, A. Balatsoukas-Stimming, T. Müller, A. Burg, C. Thibeault, and W. Gross. ACSSC, page 1194-1198. IEEE, (2016)A Wireless Body Sensor Network for Activity Monitoring with Low Transmission Overhead.R. Braojos, I. Beretta, J. Constantin, A. Burg, and D. Atienza. EUC, page 265-272. IEEE Computer Society, (2014)Statistical fault injection for impact-evaluation of timing errors on application performance.J. Constantin, A. Burg, Z. Wang, A. Chattopadhyay, and G. Karakonstantis. DAC, page 13:1-13:6. ACM, (2016)Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.I. Kazi, P. Meinerzhagen, P. Gaillardon, D. Sacchetto, Y. Leblebici, A. Burg, and G. Micheli. IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (11): 3155-3164 (2014)Approximate computing for unreliable silicon.A. Burg. DTIS, page 1. IEEE, (2016)Synthesis strategies for sub-VT systems.P. Meinerzhagen, O. Andersson, S. Sherazi, A. Burg, and J. Rodrigues. ECCTD, page 552-555. IEEE, (2011)Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes.Y. Shen, Y. Ren, A. Kristensen, A. Balatsoukas-Stimming, X. You, C. Zhang, and A. Burg. ICC, page 116-122. IEEE, (2022)

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A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.

Please choose a person to relate this publication to

Andreas Burg

Peter Burg

Peter Burg

Peter Burg

Peter Burg

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Burg, Andreas Peter"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.

Please choose a person to relate this publication to

Andreas Burg

Peter Burg

Peter Burg

Peter Burg

Peter Burg

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS.