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An adaptive cross-layer fault recovery solution for reconfigurable SoCs.

, , , and . FPT, page 188-191. IEEE, (2015)

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An automated test framework for SRAM-based FPGA., , , and . ASICON, page 1-4. IEEE, (2015)A scalable hybrid architecture for high performance data-parallel applications., , , , , and . FPT, page 191-194. IEEE, (2017)Online Task Scheduling for Heterogeneous Reconfigurable Systems., , , and . CSCWD (Selected Papers), volume 5236 of Lecture Notes in Computer Science, page 596-607. Springer, (2007)General switch box modeling and optimization for FPGA routing architectures., , , , and . FPT, page 320-323. IEEE, (2010)An on-line debug method for FPGAs., , and . ASICON, page 484-487. IEEE, (2017)High performance Deformable Part Model accelerator based on FPGA., , , , , and . FPT, page 245-248. IEEE, (2016)Fast Adjustable NPN Classification using Generalized Symmetries., , , and . FPL, page 1-7. IEEE Computer Society, (2018)MRI-based brain tumor segmentation using FPGA-accelerated neural network., , , , , , , , , and 1 other author(s). BMC Bioinform., 22 (1): 421 (2021)System Prototyping Based on SystemC Transaction-Level Modeling., , , and . IMSCCS (2), page 764-770. IEEE Computer Society, (2006)0-7695-2581-4.DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions., , , and . ICFPT, page 278-279. IEEE, (2023)