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Disambiguation of "Anderson, Jason Helge"

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Impact of FPGA architecture on resource sharing in high-level synthesis.

, , , , , , and . FPGA, page 111-114. ACM, (2012)

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Ian Jason

Hans Helge

Alexandra Helgert

Roland Helger

Thomas Helge

 

Other publications of authors with the same name

Clock power reduction for virtex-5 FPGAs., , and . FPGA, page 13-22. ACM, (2009)Impact of FPGA architecture on resource sharing in high-level synthesis., , , , , , and . FPGA, page 111-114. ACM, (2012)High-level synthesis with LegUp: a crash course for users and researchers., , , and . FPGA, page 7-8. ACM, (2013)EASY: Efficient Arbiter SYnthesis from Multi-threaded Code., , , , and . FPGA, page 142-151. ACM, (2019)Subleq⊝: An Area-Efficient Two-Instruction-Set Computer., , , and . IEEE Embed. Syst. Lett., 9 (2): 33-36 (2017)FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (9): 1305-1318 (2012)VTR 7.0: Next Generation Architecture and CAD System for FPGAs., , , , , , , , , and 4 other author(s). ACM Trans. Reconfigurable Technol. Syst., 7 (2): 6:1-6:30 (2014)The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware., , , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 8 (3): 14:1-14:26 (2015)Modulo SDC scheduling with recurrence minimization in high-level synthesis., , and . FPL, page 1-8. IEEE, (2014)From software threads to parallel hardware in high-level synthesis for FPGAs., , and . FPT, page 270-277. IEEE, (2013)