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ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning.

, , , , , , , , and . IEEE Trans. Computers, 72 (7): 1985-1998 (July 2023)

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Accurate deep neural network inference using computational phase-change memory., , , , , , , , and . CoRR, (2019)Efficient Pipelined Execution of CNNs Based on In-Memory Computing and Graph Homomorphism Verification., , , , , and . IEEE Trans. Computers, 70 (6): 922-935 (2021)ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning., , , , , , , , and . IEEE Trans. Computers, 72 (7): 1985-1998 (July 2023)11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge., , , , , , , , , and 38 other author(s). ISSCC, page 212-214. IEEE, (2024)Computational memory-based inference and training of deep neural networks., , , , , , , , , and 6 other author(s). VLSI Circuits, page 168-. IEEE, (2019)5 Parallel Prism: A topology for pipelined implementations of convolutional neural networks using computational memory., , , , , and . CoRR, (2019)Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors., , , , , , , , , and 11 other author(s). IEEE Wirel. Commun., 30 (4): 162-169 (August 2023)Accelerating Inference of Convolutional Neural Networks Using In-memory Computing., , , and . Frontiers Comput. Neurosci., (2021)Graphene-based Wireless Agile Interconnects for Massive Heterogeneous Multi-chip Processors., , , , , , , , , and 11 other author(s). CoRR, (2020)Compiling Neural Networks for a Computational Memory Accelerator., , , , , and . CoRR, (2020)