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11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.

P. Hager, B. Moons, S. Cosemans, I. Papistas, B. Rooseleer, J. Loon, R. Uytterhoeven, F. Zaruba, S. Koumousi, M. Stanisavljevic, S. Mach, S. Mutsaards, R. Aljameh, G. Khov, B. Machiels, C. Olar, A. Psarras, S. Geursen, J. Vermeeren, Y. Lu, A. Maringanti, D. Ameta, L. Katselas, N. Hütter, M. Schmuck, S. Sivadas, K. Sharma, M. Oliveira, R. Aerne, N. Sharma, T. Soni, B. Bussolino, D. Pesut, M. Pallaro, A. Podlesnii, A. Lyrakis, Y. Ruffiner, M. Dazzi, J. Thiele, K. Goetschalckx, N. Bruschi, J. Doevenspeck, B. Verhoef, S. Linz, G. Garcea, J. Ferguson, I. Koltsidas, and E. Eleftheriou. ISSCC, page 212-214. IEEE, (2024)

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Milos Horvath

Milos Jovanovic

Milos Puzovic

Alesia Miloslavina

Yuliya Miloslavina

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A Fast and Scalable Pipeline for Stain Normalization of Whole-Slide Images in Histopathology.M. Stanisavljevic, A. Anghel, N. Papandreou, S. Andani, P. Pati, J. Rüschoff, P. Wild, M. Gabrani, and H. Pozidis. ECCV Workshops (6), volume 11134 of Lecture Notes in Computer Science, page 424-436. Springer, (2018)Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density.M. Stanisavljevic, F. Gürkaynak, A. Schmid, Y. Leblebici, and M. Gabrani. ACM Great Lakes Symposium on VLSI, page 204-207. ACM, (2007)Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation.M. Stanisavljevic, A. Schmid, and Y. Leblebici. VLSI-SoC, page 328-334. IEEE, (2010)Multilevel-Cell Phase-Change Memory: A Viable Technology.A. Athmanathan, M. Stanisavljevic, N. Papandreou, H. Pozidis, and E. Eleftheriou. IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (1): 87-100 (2016)Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures.M. Stanisavljevic, A. Athmanathan, N. Papandreou, H. Pozidis, and E. Eleftheriou. IRPS, page 5. IEEE, (2015)Acceleration of Decision-Tree Ensemble Models on the IBM Telum Processor.N. Papandreou, J. van Lunteren, A. Anghel, T. Parnell, M. Petermann, M. Stanisavljevic, C. Lichtenau, A. Sica, D. Röhm, E. Tzortzatos and 1 other author(s). ISCAS, page 1-5. IEEE, (2023)Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density.M. Stanisavljevic, A. Schmid, and Y. Leblebici. IJCNN, page 2771-2778. IEEE, (2006)Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices.K. Spoon, H. Tsai, A. Chen, M. Rasch, S. Ambrogio, C. Mackin, A. Fasoli, A. Friz, P. Narayanan, M. Stanisavljevic and 1 other author(s). Frontiers Comput. Neurosci., (2021)Deep learning acceleration based on in-memory computing.E. Eleftheriou, M. Gallo, S. Nandakumar, C. Piveteau, I. Boybat, V. Joshi, R. Khaddam-Aljameh, M. Dazzi, I. Giannopoulos, G. Karunaratne and 7 other author(s). IBM J. Res. Dev., 63 (6): 7:1-7:16 (2019)A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.M. Gallo, R. Khaddam-Aljameh, M. Stanisavljevic, A. Vasilopoulos, B. Kersting, M. Dazzi, G. Karunaratne, M. Braendli, A. Singh, S. Mueller and 19 other author(s). CoRR, (2022)

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Disambiguation of "Stanisavljevic, Milos"

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11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.

Please choose a person to relate this publication to

Milos Horvath

Milos Jovanovic

Milos Puzovic

Alesia Miloslavina

Yuliya Miloslavina

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Stanisavljevic, Milos"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.

Please choose a person to relate this publication to

Milos Horvath

Milos Jovanovic

Milos Puzovic

Alesia Miloslavina

Yuliya Miloslavina

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.