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Disambiguation of "Maurine, Philippe"

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A Secure D Flip-Flop against Side Channel Attacks.

, , and . PATMOS, volume 6951 of Lecture Notes in Computer Science, page 331-340. Springer, (2011)

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Philippe Kersting

Philippe Bopp

Philippe Zysset

Philippe Moisan

Philippe Dreuw

 

Other publications of authors with the same name

Circuit sizing method under delay constraint., , , and . ISCAS, IEEE, (2006)Statistical timing characterization., , , and . ISSoC, page 1-4. IEEE, (2012)A model of the leakage in the frequency domain and its application to CPA and DPA., , , , and . J. Cryptographic Engineering, 4 (3): 197-212 (2014)CMOS Gate Sizing under Delay Constraint., , , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 60-69. Springer, (2003)Performance Metric Based Optimization Protocol., , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 100-109. Springer, (2004)Practical Analysis of RSA Countermeasures Against Side-Channel Electromagnetic Attacks., , , and . CARDIS, volume 8419 of Lecture Notes in Computer Science, page 200-215. Springer, (2013)Electromagnetic Fault Injection : How Faults Occur., , and . FDTC, page 9-16. IEEE, (2019)Method for evaluation of transient-fault detection techniques., , , , and . Microelectron. Reliab., (2017)Logical effort model extension to propagation delay representation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1677-1684 (2006)Gate Sizing for Low Power Design., , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 301-312. Kluwer, (2001)