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Design theory and implementation for low-power segmented bus systems., , , , и . ACM Trans. Design Autom. Electr. Syst., 8 (1): 38-54 (2003)DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip., , и . DAC, стр. 849-852. ACM, (2006)Fault simulation and response compaction in full scan circuits using HOPE., , , , , и . IEEE Trans. Instrumentation and Measurement, 54 (6): 2310-2328 (2005)High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols., , , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 24 (3): 1169-1173 (2016)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , и 5 other автор(ы). IEEE Des. Test Comput., 26 (1): 26-35 (2009)On random testing for combinational circuits with a high measure of confidence., и . IEEE Trans. Syst. Man Cybern., 22 (4): 748-754 (1992)Delay Fault Coverage Enhancement Using Variable Observation Times., , и . J. Electron. Test., 11 (2): 131-146 (1997)Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis., , , и . VLSI Design, 12 (4): 457-474 (2001)A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (3): 374-384 (1995)Pseudorandom test-length analysis using differential solutions., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (7): 815-825 (1996)