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Disambiguation of "Chmelar, Erik"

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Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (5): 907-918 (2007)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sylvie Chmelar

Christian Chmelar

Nilgün Erikli

Anders Erikson

Magdalena Karin Matilda Eriksson

 

Other publications of authors with the same name

Subframe multiplexing for FPGA manufacturing test configuration.. FPGA, page 245. ACM, (2004)Inconsistent Fail due to Limited Tester Timing Accuracy., , , and . VTS, page 47-52. IEEE Computer Society, (2008)Segmented Addressable Scan Architecture., , and . VTS, page 405-411. IEEE Computer Society, (2005)FPGA Interconnect Delay Fault Testing.. ITC, page 1239-1247. IEEE Computer Society, (2003)Minimizing the number of test configurations for FPGAs.. ICCAD, page 899-902. IEEE Computer Society / ACM, (2004)Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (5): 907-918 (2007)Session Abstract., and . VTS, page 156-157. IEEE Computer Society, (2006)FPGA Bridging Fault Detection and Location via Differential IDDQ., and . VTS, page 109-116. IEEE Computer Society, (2004)