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Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware.

, , and . ARC, volume 4419 of Lecture Notes in Computer Science, page 110-121. Springer, (2007)

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Hybrid-Mode Floating-Point FPGA CORDIC Co-processor., , , and . ARC, volume 4943 of Lecture Notes in Computer Science, page 254-259. Springer, (2008)Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor., , , , and . HPCC, page 182-189. IEEE Computer Society, (2008)VLIW coprocessor for IEEE-754 quadruple-precision elementary functions., , , , , , and . ACM Trans. Archit. Code Optim., 10 (3): 12:1-12:22 (2013)A Parameterized Architecture Model in High Level Synthesis for Image Processing Applications., and . ASP-DAC, page 523-528. IEEE Computer Society, (2007)Pipeline template and scheduling algorithm for mapping multiple loop nests on FPGA with limited resources., , and . ACM Great Lakes Symposium on VLSI, page 343-344. ACM, (2013)Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA., , , and . ICESS, page 616-620. IEEE Computer Society, (2008)Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware., , and . ARC, volume 4419 of Lecture Notes in Computer Science, page 110-121. Springer, (2007)Designing a Coarse-Grained Reconfigurable Architecture Using Loop Self-Pipelining., , , and . Asia-Pacific Computer Systems Architecture Conference, volume 4186 of Lecture Notes in Computer Science, page 567-573. Springer, (2006)