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Disambiguation of "Azarderakhsh, Reza"

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Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures.

, , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (2): 125-129 (2014)

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Leila Rezaizadehnajafi

Majid Reza

Fereidoun Rezanezhad

Kianoosh Rezania

Majid Rezaei

 

Other publications of authors with the same name

Fast Inversion in $GF(2^m)$ with Normal Basis Using Hybrid-Double Multipliers., , and . IEEE Trans. Computers, 63 (4): 1041-1047 (2014)Optimized SIKE Round 2 on 64-bit ARM., , and . WISA, volume 11897 of Lecture Notes in Computer Science, page 341-353. Springer, (2019)Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (12): 2804-2812 (2015)Modeling Quantum-Safe Authenticated Key Establishment, and an Isogeny-Based Protocol., , and . IACR Cryptology ePrint Archive, (2018)Supersingular Isogeny Key Encapsulation (SIKE) Round 2 on ARM Cortex-M4., , , and . IACR Cryptology ePrint Archive, (2020)High-Performance Implementation of Point Multiplication on Koblitz Curves., and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (1): 41-45 (2013)Optimized Implementation of SIKE Round 2 on 64-bit ARM Cortex-A Processors., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (8): 2659-2671 (2020)A High-Performance and Scalable Hardware Architecture for Isogeny-Based Cryptography., , and . IEEE Trans. Computers, 67 (11): 1594-1609 (2018)Error Detection Constructions for ITA Finite Field Inversions Over $GF(2^m)$ on FPGA Using CRC and Hamming Codes., , and . IEEE Trans. Reliab., 72 (2): 651-661 (2023)Cryptographic Accelerators for Digital Signature Based on Ed25519., , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (7): 1297-1305 (2021)