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Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems.

, , , , and . CoRR, (2018)

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A Stable Switched-System Approach to Collision-Free Wheeled Mobile Robot Navigation., , , , and . Journal of Intelligent and Robotic Systems, 86 (3-4): 599-616 (2017)Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems., , , , and . CoRR, (2018)Linearly compressed pages: a low-complexity, low-latency main memory compression framework., , , , , , , and . MICRO, page 172-184. ACM, (2013)Reducing DRAM Refresh Overheads with Refresh-Access Parallelism., , , , , , and . CoRR, (2018)Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism., , , , and . CoRR, (2018)An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms., , , , and . ISCA, page 60-71. ACM, (2013)Tiered-latency DRAM: A low latency and low cost DRAM architecture., , , , , and . HPCA, page 615-626. IEEE Computer Society, (2013)A case for exploiting subarray-level parallelism (SALP) in DRAM., , , , and . ISCA, page 368-379. IEEE Computer Society, (2012)Half-Double: Hammering From the Next Row Over., , , , , , , , and . USENIX Security Symposium, page 3807-3824. USENIX Association, (2022)Tiered-Latency DRAM (TL-DRAM)., , , , , and . CoRR, (2016)