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FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder., , , , and . Circuits and Systems, 1 (1): 18-29 (2010)HW/SW FPGA Architecture for a Flexible Motion Estimation., , , and . ICECS, page 30-33. IEEE, (2007)FPGA architecture of the LDPS Motion Estimation for H.264/AVC Video Coding., , , , , and . J. Signal Process. Syst., 68 (2): 273-285 (2012)A SIP-Based Programming Framework for Advanced Telephony Applications., , , and . IPTComm, volume 5310 of Lecture Notes in Computer Science, page 1-20. Springer, (2008)FPGA implementation of a HW/SW platform for multimedia embedded systems., , , and . Des. Autom. Embed. Syst., 12 (4): 293-311 (2008)Optimization and Implementation on Fpga of the DCT/IDCT Algorithm., , , , , and . ICASSP (3), page 928-931. IEEE, (2006)An Efficient HW/SW Implementation of the H.263 Video Coder in FPGA., , , , , and . ICECS, page 814-817. IEEE, (2006)HW/SW Codesign of the H.263 Video Coder., , , , , and . CCECE, page 783-787. IEEE, (2006)A Very High Throughput Deblocking Filter for H.264/AVC., , , and . J. Signal Process. Syst., 73 (2): 189-199 (2013)HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter., , , , and . Int. Arab J. Inf. Technol., 7 (1): 70-74 (2010)