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An Overview of a Compiler for Mapping Software Binaries to Hardware.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (11): 1177-1190 (2007)

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An Overview of a Compiler for Mapping Software Binaries to Hardware., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (11): 1177-1190 (2007)Overview of a compiler for synthesizing MATLAB programs onto FPGAs., , , , , , , , , and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 12 (3): 312-324 (2004)A Linear Algebra Framework for Automatic Determination of Optimal Data Layouts., , , , and . IEEE Trans. Parallel Distributed Syst., 10 (2): 115-135 (1999)A Layout-Conscious Iteration Space Transformation Technique., , , and . IEEE Trans. Computers, 50 (12): 1321-1336 (2001)Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 447-455 (2007)Implications of VHDL timing models on simulation and software synthesis., , and . J. Syst. Archit., 44 (1): 23-36 (1997)An evaluation of parallel simulated annealing strategies with application to standard cell placement., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (4): 398-410 (1997)Parallel algorithms for VLSI circuit extraction., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (5): 604-618 (1991)Parallel construction algorithms for BDDs., and . ISCAS (1), page 318-322. IEEE, (1999)A Matrix-Based Approach to the Global Locality Optimization Problem., , , and . IEEE PACT, page 306-313. IEEE Computer Society, (1998)