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Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.

G. Miñana, O. Garnica, J. Hidalgo, J. Lanchares, and J. Colmenar. PATMOS, volume 3728 of Lecture Notes in Computer Science, page 40-48. Springer, (2005)

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Elena Pérez-Miñana

Guadalupe Sánchez

Guadalupe Arredondo Arreola

Guadalupe Sanchez Kleele

Guadalupe Munoz-Baca

Other publications of authors with the same name

Memories in Complutense Campus.V. López, M. Peñas, G. Miñana, R. Caro, S. Kraemmer, M. Balmaseda, and G. Juan. A Tribute to Prof. Dr. Da Ruan, page 143-150. Springer, (2013)Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.G. Miñana, O. Garnica, J. Hidalgo, J. Lanchares, and J. Colmenar. PATMOS, volume 3728 of Lecture Notes in Computer Science, page 40-48. Springer, (2005)A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.G. Miñana, J. Hidalgo, O. Garnica, J. Lanchares, J. Colmenar, and S. López. PATMOS, volume 4148 of Lecture Notes in Computer Science, page 514-523. Springer, (2006)Comparing the Performance of a 64-bit Fully-Asynchronous Superscalar Processor versus its Synchronous Counterpart.J. Colmenar, O. Garnica, J. Lanchares, J. Hidalgo, G. Miñana, and S. López. DSD, page 423-432. IEEE Computer Society, (2006)Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions.J. Colmenar, O. Garnica, J. Lanchares, J. Hidalgo, G. Miñana, and S. López. Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 495-505. Springer, (2006)A Power-Aware Technique for Functional Units in High-Performance Processors.G. Miñana, O. Garnica, J. Hidalgo, J. Lanchares, and J. Colmenar. DSD, page 456-459. IEEE Computer Society, (2006)Enhancing Students' Learning Process Through Self-Generated Tests.M. Sánchez-Élez, I. Pardines, P. García, G. Miñana, S. Navarro, M. Sánchez, and J. Risco-Martín. CoRR, (2024)Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders.G. Miñana, J. Hidalgo, J. Lanchares, J. Colmenar, O. Garnica, and S. López. IET Comput. Digit. Tech., 1 (2): 113-119 (2007)

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Disambiguation of "Miñana, Guadalupe"

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Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.

Please choose a person to relate this publication to

Elena Pérez-Miñana

Guadalupe Sánchez

Guadalupe Arredondo Arreola

Guadalupe Sanchez Kleele

Guadalupe Munoz-Baca

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Miñana, Guadalupe"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.

Please choose a person to relate this publication to

Elena Pérez-Miñana

Guadalupe Sánchez

Guadalupe Arredondo Arreola

Guadalupe Sanchez Kleele

Guadalupe Munoz-Baca

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width.