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Mapping and Topology Customization Approaches for Application-Specific STNoC Designs.

, , , , and . ASAP, page 61-68. IEEE Computer Society, (2007)

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Error resilience of intra-die and inter-die communication with 3D spidergon STNoC., , , , and . DATE, page 275-278. IEEE Computer Society, (2010)Permanent Scatterers: precision assessment and multi-platform analysis., , , , and . IGARSS, page 1193-1195. IEEE, (2003)Design methodologies and advanced architectures for system on chip platforms: focus on communication.. University of Pisa, Italy, (2004)Skew Insensitive Physical Links for Network on Chip., , , , , , , and . Nano-Net, page 1-5. IEEE, (2006)Design and Implementation on FPGA of a HW Accelerator for Post-Quantum RLWE Polynomial Operations., , and . ApplePies, volume 1036 of Lecture Notes in Electrical Engineering, page 57-64. Springer, (2022)Application-Specific Topology Design Customization for STNoC., , , , and . DSD, page 547-550. IEEE Computer Society, (2007)A reusable coverage-driven verification environment for Network-on-Chip communication in embedded system platforms., , , , , , , and . WISES, page 71-77. IEEE, (2009)Spidergon: a novel on-chip communication network., , , , and . SoC, IEEE, (2004)EEEP: an extreme end to end flow control protocol for SDRAM access through networks on chip., , , and . INA-OCMC@HiPEAC, page 3-6. ACM, (2011)Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip., , , , , , , and . IEEE Trans. Computers, 57 (9): 1196-1201 (2008)