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1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.

, , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 40 (4): 862-869 (2005)

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