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LFSROM an algorithm for automatic design synthesis of hardware test pattern generator.

, , and . VTS, page 208-214. IEEE Computer Society, (1993)

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Distributed asynchronous controllers for clock management in low power systems., , , , , and . ICECS, page 379-382. IEEE, (2014)HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization., , , , and . J. Circuits Syst. Comput., 26 (8): 1740004:1-1740004:19 (2017)A hybrid power modeling approach to enhance high-level power models., , , , and . DDECS, page 151-156. IEEE, (2016)A generic clock controller for low power systems: Experimentation on an AXI bus., , , , , and . VLSI-SoC, page 307-312. IEEE, (2015)BIST hardware generator for mixed test scheme., , and . ED&TC, page 424-430. IEEE Computer Society, (1995)LFSROM an algorithm for automatic design synthesis of hardware test pattern generator., , and . VTS, page 208-214. IEEE Computer Society, (1993)A Hybrid Power Estimation Technique to improve IP power models quality., , , , and . VLSI-SoC, page 1-6. IEEE, (2016)An efficient hybrid power modeling approach for accurate gate-level power estimation., , , , and . ICM, page 17-20. IEEE, (2015)A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality., , , , and . J. Low Power Electron., 13 (1): 10-28 (2017)