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CryoCMOS hardware technology a classical infrastructure for a scalable quantum computer.

, , , , , , , , and . Conf. Computing Frontiers, page 282-287. ACM, (2016)

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Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computers., , , , , , , , , and 1 other author(s). ISCAS, page 1-5. IEEE, (2019)Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited., , , , , , , , and . DAC, page 13:1-13:6. ACM, (2017)200 MS/s ADC implemented in a FPGA employing TDCs., , and . FPGA, page 228-235. ACM, (2015)Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures., and . FPT, page 25-31. IEEE, (2017)Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS., , , and . IEEE SENSORS, page 1-3. IEEE, (2016)A 1 GSa/s, Reconfigurable Soft-core FPGA ADC (Abstract Only)., , and . FPGA, page 281. ACM, (2016)CryoCMOS hardware technology a classical infrastructure for a scalable quantum computer., , , , , , , , and . Conf. Computing Frontiers, page 282-287. ACM, (2016)Cryogenic CMOS interfaces for quantum devices., , , , , , , , and . IWASI, page 59-62. IEEE, (2017)Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures., , , , , and . ESSDERC, page 58-61. IEEE, (2017)15.5 Cryo-CMOS circuits and systems for scalable quantum computing., , , , , , , , , and 2 other author(s). ISSCC, page 264-265. IEEE, (2017)