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Disambiguation of "Silberman, Joel"

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Reducing Power Consumption during TLB Lookups in a PowerPC Embedded Processor.

, , , and . ISQED, page 54-58. IEEE Computer Society, (2005)

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Rosa Silberman

Artur Joel

Walter Joel

Feiga Joelsohn

Hans Joël

 

Other publications of authors with the same name

Designing for a gigahertz guTS integer processor., , , , , , , and . IEEE Micro, 18 (3): 66-74 (1998)Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI., , , , , , , , , and 19 other author(s). IBM J. Res. Dev., 51 (5): 529-544 (2007)The circuit design of the synergistic processor element of a CELL processor., , , , , , , , , and 3 other author(s). ICCAD, page 111-117. IEEE Computer Society, (2005)A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling., , , , , , , , , and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)A 690 ps read-access latency register file for a GHz integer microprocessor., , , , and . ICCD, page 6-10. IEEE Computer Society, (1998)A 1.0-GHz single-issue 64-bit powerPC integer processor., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 33 (11): 1600-1608 (1998)Efficient AI System Design With Cross-Layer Approximate Computing., , , , , , , , , and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)Power-Conscious Design of the Cell Processor's Synergistic Processor Element., , , , and . IEEE Micro, 25 (5): 10-18 (2005)"Timing closure by design, " a high frequency microprocessor design methodology., , , , , , , , , and 7 other author(s). DAC, page 712-717. ACM, (2000)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling., , , , , , , , , and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)