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Disambiguation of "Kawasumi, Atsushi"

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The circuit design of the synergistic processor element of a CELL processor.

, , , , , , , , , , , , and . ICCAD, page 111-117. IEEE Computer Society, (2005)

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Atsushi Imai

Atsushi Imai

Atsushi Yagi

Atsushi Fukui

Atsushi Kambayashi

 

Other publications of authors with the same name

Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor., , , , , , , , and . IEEE Micro, 25 (5): 30-38 (2005)Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme., , , and . A-SSCC, page 165-168. IEEE, (2011)A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs., , , , , , , and . VLSIC, page 100-101. IEEE, (2012)Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (5): 294-298 (2011)Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges., , , , , , and . IEEE J. Solid State Circuits, 48 (4): 924-931 (2013)Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction., , , , , , , and . ICICDT, page 1-4. IEEE, (2012)A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges., , , , , , and . VLSIC, page 60-61. IEEE, (2012)Introduction to the Special Section on the 2019 Asian Solid-State Circuits Conference (A-SSCC)., , and . IEEE J. Solid State Circuits, 55 (10): 2627-2628 (2020)A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 49 (1): 118-126 (2014)7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme., , , , , , , , , and 3 other author(s). ISSCC, page 132-133. IEEE, (2016)