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A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.

T. Tambe, J. Zhang, C. Hooper, T. Jia, P. Whatmough, J. Zuckerman, M. dos Santos, E. Loscalzo, D. Giri, K. Shepard, L. Carloni, A. Rush, D. Brooks, and G. Wei. ISSCC, page 342-343. IEEE, (2023)

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Shibashish Giri

Wolfgang Girisch

Joseph Girisch

Philipp Girichidis

Jana Girisch

Other publications of authors with the same name

Accelerators and Coherence: An SoC Perspective.D. Giri, P. Mantovani, and L. Carloni. IEEE Micro, 38 (6): 36-45 (2018)The MosaicSim Simulator (Full Technical Report).O. Matthews, A. Manocha, D. Giri, M. Orenes-Vera, E. Tureci, T. Sorensen, T. Ham, J. Aragón, L. Carloni, and M. Martonosi. CoRR, (2020)SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs.G. Tombesi, J. Zuckerman, P. Mantovani, D. Giri, M. dos Santos, T. Jia, D. Brooks, G. Wei, and L. Carloni. IEEE Des. Test, 40 (6): 64-75 (December 2023)DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.F. Gao, T. Chang, A. Li, M. Orenes-Vera, D. Giri, P. Jackson, A. Ning, G. Tziantzioulis, J. Zuckerman, J. Tu and 7 other author(s). CICC, page 1-2. IEEE, (2023)A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.M. dos Santos, T. Jia, M. Cochet, K. Swaminathan, J. Zuckerman, P. Mantovani, D. Giri, J. Zhang, E. Loscalzo, G. Tombesi and 8 other author(s). ICCAD, page 20:1-20:9. ACM, (2022)Agile SoC Development with Open ESP : Invited Paper.P. Mantovani, D. Giri, G. Guglielmo, L. Piccolboni, J. Zuckerman, E. Cota, M. Petracca, C. Pilato, and L. Carloni. ICCAD, page 96:1-96:9. IEEE, (2020)PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs.B. Seyoum, D. Giri, K. Chiu, B. Natter, and L. Carloni. DATE, page 1-6. IEEE, (2023)Runtime reconfigurable memory hierarchy in embedded scalable platforms.D. Giri, P. Mantovani, and L. Carloni. ASP-DAC, page 719-726. ACM, (2019)Accelerators & Security: The Socket Approach.L. Piccolboni, D. Giri, and L. Carloni. IEEE Comput. Archit. Lett., 21 (2): 65-68 (2022)Parallel and Serial Computation in Nanomagnet Logic: An Overview.D. Giri, G. Causapruno, and F. Riente. IEEE Trans. Very Large Scale Integr. Syst., 26 (8): 1427-1437 (2018)

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Disambiguation of "Giri, Davide"

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A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.

Please choose a person to relate this publication to

Shibashish Giri

Wolfgang Girisch

Joseph Girisch

Philipp Girichidis

Jana Girisch

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Giri, Davide"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.

Please choose a person to relate this publication to

Shibashish Giri

Wolfgang Girisch

Joseph Girisch

Philipp Girichidis

Jana Girisch

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management.