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Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance., , , , and . IEEE Micro, 24 (6): 62-73 (2004)Transactional memory and the birthday paradox., and . SPAA, page 303-304. ACM, (2007)Improving the Throughput of Synchronization by Insertion of Delays., , and . HPCA, page 168-179. IEEE Computer Society, (2000)An Architectural Evaluation of Java TPC-W., , , and . HPCA, page 229-240. IEEE Computer Society, (2001)Transactional Memory, 2nd Edition, , and . Synthesis Lectures on Computer Architecture Morgan & Claypool Publishers, (2010)Towards an Adaptable Systems Architecture for Memory Tiering at Warehouse-Scale., , , , , , , , , and 8 other author(s). ASPLOS (3), page 727-741. ACM, (2023)Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors., , and . MICRO, page 423-. IEEE Computer Society, (2003)Scalable Load and Store Processing in Latency-Tolerant Processors., , , , and . IEEE Micro, 26 (1): 30-39 (2006)Performance evaluation of Intel® transactional synchronization extensions for high-performance computing., , , and . SC, page 19:1-19:11. ACM, (2013)Inferential queueing and speculative push for reducing critical communication latencies., , and . ICS, page 273-284. ACM, (2003)