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Spur reduction in wideband PLLs by random positioning of charge pump current pulses., and . ISCAS, page 3397-3400. IEEE, (2010)Electronic time stretching for fast digitization.. ISCAS, page 1391-1394. IEEE, (2011)A 12.5 mW, 11.1 nV√Hz, -115 dB THD, Settling, 18 bit SAR ADC Driver in 0.6 µm CMOS., , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (5): 443-447 (2016)Micropower low-voltage analog filter in a digital CMOS process., and . IEEE J. Solid State Circuits, 38 (6): 1063-1067 (2003)A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS., and . IEEE J. Solid State Circuits, 35 (7): 1019-1024 (2000)Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)., , , , and . IEEE J. Solid State Circuits, 56 (12): 3547-3550 (2021)Oversampling Analog-to-Digital Converter Design., and . VLSI Design, page 7. IEEE Computer Society, (2008)Negative Feedback System and Circuit Design., and . VLSI Design, page 35-36. IEEE Computer Society, (2009)Simulation of Divider Phase Noise and Spurious Tones in Integer-N PLLs., and . ICECS, page 1-5. IEEE, (2023)Settling Time Reduction in a Phase-Locked Loop using Pre-emphasis., and . APCCAS, page 11-15. IEEE, (2023)