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A Case Study for Improving Performances of Deep-Learning Processor with MRAM., , , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2024)A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current., , and . IEEE J. Solid State Circuits, 35 (10): 1498-1501 (2000)Signal contributions to heavily diffusion-weighted functional magnetic resonance imaging investigated with multi-SE-EPI acquisitions., , , , , , , and . NeuroImage, (2014)A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations., , , , , , , , , and . IEEE J. Sel. Top. Signal Process., 14 (4): 634-645 (2020)Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks., , , , , and . IEICE Trans. Commun., 89-B (10): 2741-2751 (2006)A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture., , , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3623-3633 (2006)A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2226-2233 (2012)STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier., , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 97-A (12): 2411-2417 (2014)A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing., , , , , , , and . IEICE Trans. Electron., 91-C (4): 543-552 (2008)Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure., , , , and . IEICE Trans. Electron., 95-C (10): 1675-1681 (2012)