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Disambiguation of "Matsukawa, Go"

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A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme.

, , , , , , , , and . IEICE Trans. Electron., 98-C (4): 333-339 (2015)

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GO

Minoru Matsukawa

Kohan Go

Bansing Go

Li-mei Go

 

Other publications of authors with the same name

A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations., , , , , , , , , and . IEEE J. Sel. Top. Signal Process., 14 (4): 634-645 (2020)Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (6): 1198-1205 (2016)Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path., , , , , and . ATS, page 139-144. IEEE Computer Society, (2015)An soft error propagation analysis considering logical masking effect on re-convergent path., , , , and . IOLTS, page 13-16. IEEE, (2016)FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature., , , , , , , , , and . SiPS, page 1-6. IEEE, (2017)A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme., , , , , , , , and . IEICE Trans. Electron., 98-C (4): 333-339 (2015)A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video., , , , , , , , , and . IEICE Electron. Express, 14 (15): 20170668 (2017)A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668., , , , , , , , , and . IEICE Electron. Express, 15 (12): 20188003 (2018)An accurate soft error propagation analysis technique considering temporal masking disablement., , , , , and . IOLTS, page 23-25. IEEE, (2015)A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM., , , , , , , and . ARCS Workshops, page 1-5. VDE Verlag / IEEE Xplore, (2014)