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Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (11): 2256-2267 (2014)Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications., , , , and . IEEE Access, (2020)Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems., , , and . CSSP, 38 (4): 1793-1810 (2019)Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension., , , , and . IEEE Trans. Aerosp. Electron. Syst., 59 (5): 5835-5846 (October 2023)Design and implementation of efficient QCA full-adders using fault-tolerant majority gates., , , , and . J. Supercomput., 78 (6): 8056-8080 (2022)Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes., , , and . IEEE Access, (2021)Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs., , , and . IEEE Access, (2021)Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale., , , , and . IEEE Trans. Emerg. Top. Comput., 10 (2): 635-647 (2022)Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories., , and . IEEE Trans. Emerg. Top. Comput., 9 (4): 2139-2145 (2021)RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography., , , and . IEEE Trans. Computers, 72 (3): 682-692 (March 2023)