Author of the publication

A Testable/Fault Tolerant FFT Processor Design.

, , and . Asian Test Symposium, page 429-. IEEE Computer Society, (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Combinational circuit fault diagnosis using logic emulation., , , , and . ISCAS (5), page 549-552. IEEE, (2003)Efficient test and repair architectures for 3D TSV-based random access memories., , , and . VLSI-DAT, page 1-4. IEEE, (2013)Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs., , , and . VLSI-DAT, page 1-4. IEEE, (2015)A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume., , , , and . ISCIT, page 1-5. IEEE, (2017)Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults., , , , , and . J. Inf. Sci. Eng., 19 (4): 571-587 (2003)A built-in supply current test circuit for electrical interconnect tests of 3D ICs., , , and . 3DIC, page 1-6. IEEE, (2014)Defect Level Prediction Using Multi-Model Fault Coverage.. IEICE Trans. Inf. Syst., 87-D (6): 1488-1495 (2004)A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs., , , , , , and . IEICE Trans. Inf. Syst., 99-D (11): 2723-2733 (2016)A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs., , , , and . IEICE Trans. Inf. Syst., 101-D (8): 2053-2063 (2018)Yield enhancement techniques for 3-dimensional random access memories., , and . Microelectron. Reliab., 52 (6): 1065-1070 (2012)