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Disambiguation of "Stanger, Inbal"

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Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET.

, , , , and . ISCAS, page 1. IEEE, (2021)

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Inbal Yahav

Margot Stanger

Christian Stanger

Bernd Stanger

Sebastian Stanger

 

Other publications of authors with the same name

Evaluation of Dual Mode Logic Under Cryogenic Temperatures., , , , , , , and . ISCAS, page 361-364. IEEE, (2022)A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic., , , , , and . IEEE J. Solid State Circuits, 57 (2): 596-608 (2022)Overview of Cryogenic Operation in Nanoscale Technology Nodes., , , , , and . LASCAS, page 1-4. IEEE, (2023)Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths., , , , and . ISCAS, page 1. IEEE, (2021)Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance., , , , , and . ISCAS, page 1-5. IEEE, (2020)Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology., , , , , and . ISCAS, page 1-5. IEEE, (2020)Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET., , , , and . ISCAS, page 1. IEEE, (2021)Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 71 (3): 987-999 (March 2024)Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (9): 1639-1643 (2020)Dual Mode Logic Address Decoder., , , , and . ISCAS, page 1-5. IEEE, (2020)