( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs.

, и . J. Electron. Test., 4 (3): 267-281 (1993)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Egor Dranischnikow

Alexei Egorov

Dassia Egorova

Fedor Egorov

Wenedikt Egorow

 

Другие публикации лиц с тем же именем

A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST., и . J. Electron. Test., 8 (2): 165-177 (1996)A new method for correcting time and soft errors in combinational circuits., , и . DDECS, стр. 283-286. IEEE Computer Society, (2013)A linear code-preserving signature analyzer COPMISR., , и . VTS, стр. 350-355. IEEE Computer Society, (1997)Self-Checking Comparator with One Periodic Output., , , и . IEEE Trans. Computers, 45 (3): 379-380 (1996)Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead., , и . IOLTW, стр. 147-152. IEEE Computer Society, (2001)A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes., , и . Asian Test Symposium, стр. 365-. IEEE Computer Society, (2001)Design of Self-Parity Combinational Circuits for Self-testing and On-line Detection., и . DFT, стр. 239-246. IEEE Computer Society, (1993)Code-Disjoint Circuits for Parity Circuits., , и . Asian Test Symposium, стр. 100-. IEEE Computer Society, (1997)Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems., и . VTS, стр. 138-144. IEEE Computer Society, (1996)A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing., , и . VTS, стр. 324-331. IEEE Computer Society, (1998)