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Design of Self-Parity Combinational Circuits for Self-testing and On-line Detection.

, and . DFT, page 239-246. IEEE Computer Society, (1993)

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Memories for Parallel Subtree-Access., and . Parallel Algorithms and Architectures, volume 269 of Lecture Notes in Computer Science, page 122-130. Springer, (1987)Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors., , and . IOLTS, page 116-121. IEEE, (2014)Zur Verarbeitung von Zufallsfolgen durch abstrakte Automaten II., and . Elektronische Informationsverarbeitung und Kybernetik, 9 (9): 549-567 (1973)Zur Verarbeitung von Zufallsfolgen durch abstrakte Automaten I., and . Elektronische Informationsverarbeitung und Kybernetik, 9 (7/8): 433-454 (1973)Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs., and . J. Electron. Test., 4 (3): 267-281 (1993)Self-checking Carry-selectAdder with Sum-bit Duplication., , , and . ARCS Workshops, volume P-41 of LNI, page 84-91. GI, (2004)Test set enrichment using a probabilistic fault model and the theory of output deviations., , and . DATE, page 1270-1275. European Design and Automation Association, Leuven, Belgium, (2006)Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design., and . VTS, page 151-157. IEEE Computer Society, (1994)New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability., , and . IOLTS, page 37-42. IEEE Computer Society, (2008)Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits., , , and . IOLTS, page 35-. IEEE Computer Society, (2003)