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Disambiguation of "Choi, Hyojin"

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Performance analysis of multi-bank DRAM with increased clock frequency.

, , , and . ISCAS, page 2477-2480. IEEE, (2012)

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Andreas Choi

Chiwon Choi

Carmen Choi

Jinsub Choi

Bongkyung Choi

 

Other publications of authors with the same name

Demo: Human-Interactive Hardware-In-the-Loop Simulator for Cooperative Intelligent Transportation Systems and services., , , , , , , , and . VNC, page 169-170. IEEE, (2015)Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data Encoding., , and . ISCAS, page 2898-2901. IEEE, (2007)Poster: Development of ICA algorithm for V2X communications by using PreScan., , , and . VNC, page 167-168. IEEE, (2015)VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 843-847 (2010)Memory access pattern-aware DRAM performance model for multi-core systems., , and . ISPASS, page 66-75. IEEE Computer Society, (2011)A simulation-based study for DRAM power reduction strategies in GPGPUs., , , and . ISCAS, page 1343-1346. IEEE, (2012)Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP., , and . J. Signal Process. Syst., 51 (3): 289-302 (2008)Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs., , , , , , , , , and 2 other author(s). DAC, page 523-528. IEEE, (2021)Reducing off-chip memory traffic by selective cache management scheme in GPGPUs., , and . GPGPU@ASPLOS, page 110-119. ACM, (2012)Fast Block Mode Decision for H.264/AVC on a Programmable Digital Signal Processor., , and . SiPS, page 169-174. IEEE, (2007)