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Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications.

, , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (7): 2345-2357 (2020)

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Design of High Performance 8 bit Multiplier using Vedic Multiplication Algorithm with McCMOS Technique., , , and . J. Signal Process. Syst., 76 (1): 1-9 (2014)EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control., and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2142-2151 (2016)Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM., , and . J. Low Power Electron., 4 (2): 158-168 (2008)SMS-CAM: Shared matchline scheme for content addressable memory., , , and . Integr., (2023)Match-line control unit for power and delay reduction in hybrid CAM., , , and . IET Circuits Devices Syst., 15 (3): 272-283 (2021)ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics., , , and . Microelectron. J., 42 (12): 1343-1352 (2011)A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access., , , and . VLSID, page 341-346. IEEE Computer Society, (2017)Low-power content addressable memory design using two-layer P-N match-line control and sensing., , , and . Integr., (2020)A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (11): 1910-1920 (2016)A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (5): 1591-1601 (2018)