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Disambiguation of "Bonetti, Andrea"

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Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space.

, , , , , and . IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 67-I (4): 1207-1217 (2020)

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Federico Bonetti

Giocondo Bonetti

Yargo Bonetti

Andreas Facco Bonetti

Andrea Witzenrath

Risikofaktoren für abdominelle Komplikationen nach kardiopulmonalem Bypass. Uni Erlangen-Nürnberg, (2009)
 

Other publications of authors with the same name

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications., , , , , , and . A-SSCC, page 219-222. IEEE, (2019)Data-Retention-Time Characterization of Gain-Cell eDRAMs Across the Design and Variations Space., , and . ISCAS, page 1-5. IEEE, (2019)GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI., , , and . ISCAS, page 1. IEEE, (2020)Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2388-2400 (2017)Gain-Cell Embedded DRAMs: Modeling and Design Space., , , , and . ISCAS, page 1. IEEE, (2020)A tool for the assisted design of charge redistribution SAR ADCs., , , and . DATE, page 1265-1268. ACM, (2015)DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment., , , , , and . ESSCIRC, page 261-264. IEEE, (2016)Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs., , , , , , , and . EMBC, page 6978-6981. IEEE, (2021)A simulation and modeling environment for the analysis and design of charge redistribution DACs used in SAR ADCs., , , and . MIPRO, page 74-79. IEEE, (2014)An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop., , and . ISCAS, page 1850-1853. IEEE, (2015)