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Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers.

, и . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (3): 1057-1070 (марта 2023)

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Digital signal Processor-based Investigation of Chua's Circuit family., , , и . Chua's Circuit, том 1 из World Scientific Series on Nonlinear Science Series B, World Scientific, (1993)Comments on "folding of phase noise spectra in charge-pump phase-locked loops induced by frequency division"., , и . ICECS, стр. 612-615. IEEE, (2016)First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter., , и . ICECS, стр. 41-44. IEEE, (2010)Spurious tones in digital delta-sigma modulators resulting from pseudorandom dither., , и . J. Frankl. Inst., 352 (8): 3325-3344 (2015)Estimating the locking range of analog dividers through a phase-domain macromodel., , , и . ISCAS, стр. 1535-1538. IEEE, (2010)Mitigation of "Horn Spurs" in a MASH-Based Fractional-N CP-PLL., и . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (5): 821-825 (2020)A Family of ΔΣ Modulators With High Spur Immunity and Low Folded Nonlinearity Noise When Used in Fractional- Frequency Synthesizers., и . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (11): 4499-4509 (2022)Folded Noise Prediction in Nonlinear Fractional-N Frequency Synthesizers., и . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (10): 4038-4048 (2021)An equation for Generating Chaos and its monolithic Implementation., , и . Int. J. Bifurc. Chaos, 12 (12): 2885-2895 (2002)Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part II: SQ-DDSM., и . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (2): 112-116 (2009)