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Disambiguation of "Yoshida, Eiji"

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A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE.

, , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 49 (12): 2915-2924 (2014)

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Eiji Hisamatsu

Eiji Habuto

Daisuke Yoshida

Takuro Yoshida

Shingo Yoshida

 

Other publications of authors with the same name

Application of IEC61131-3 for semiconductor processing equipment., , , , and . ETFA (2), page 47-50. IEEE, (2001)0-7803-7241-7.Invariant Codes for Similar Transformation and its Application to Shape Matching., and . VISAPP (2), page 264-269. INSTICC - Institute for Systems and Technologies of Information, Control and Communication, (2008)978-989-8111-21-0.NVKVS: Non-Volatile Memory Optimized Key-Value Separated LSM-Tree., , , , , and . J. Inf. Process., (2022)Offline Quantum Circuit Pruning for Quantum Chemical Calculations., , and . QCE, page 349-355. IEEE, (2023)Cost-Performance Evaluation of Heterogeneous Tierless Storage Management in a Public Cloud., , , , and . CANDAR, page 121-126. IEEE, (2021)Reducing CPU Power Consumption for Low-Latency SSDs., and . NVMSA, page 79-84. IEEE, (2018)A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 49 (12): 2915-2924 (2014)Ultra-High Capacity Optical Transmission Technologies for 100 Tbit/s Optical Transport Networks., , , and . IEICE Trans. Commun., 94-B (2): 400-408 (2011)Compact ROSA for 100-Gb/s (4 × 25 Gb/s) Ethernet with a PLC-based AWG demultiplexer., , , , , , , and . OFC/NFOEC, page 1-3. IEEE, (2013)3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE., , , , , , , , , and 5 other author(s). ISSCC, page 60-61. IEEE, (2014)