Author of the publication

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE.

, , , , , , , , , , , , , , and . ISSCC, page 60-61. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process., , , , , , , , , and . CICC, page 131-134. IEEE, (2005)A CMOS multichannel 10-Gb/s transceiver., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 38 (12): 2094-2100 (2003)A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 40 (4): 978-985 (2005)A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 49 (12): 2915-2924 (2014)3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE., , , , , , , , , and 5 other author(s). ISSCC, page 60-61. IEEE, (2014)