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Disambiguation of "Sinha, Debjit"

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Yield-Aware Cache Architectures.

, , , , and . MICRO, page 15-25. IEEE Computer Society, (2006)

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Prashant Sinha

Intermediate states in bivalent ion induced shrinking of polyacrylate coils on surfaces and in solution. TU Dresden, (2009)

Vineet Sinha

Jyoti Sinha

Rileen Sinha

Raunak Sinha

 

Other publications of authors with the same name

Driver waveform computation for timing analysis with multiple voltage threshold driver models., , , , , and . DAC, page 425-428. ACM, (2008)Statistical Timing Analysis considering Multiple-Input Switching., , , , , , and . DAC, page 1-6. IEEE, (2020)Statistical Timing Yield Optimization by Gate Sizing., , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (10): 1140-1146 (2006)Gate-size optimization under timing constraints for coupling-noise reduction., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1064-1074 (2006)Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (3): 447-455 (2007)Constrained aggressor set selection for maximum coupling noise., , , , and . ICCAD, page 790-796. IEEE Computer Society, (2008)Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation., and . ICCAD, page 14-19. IEEE Computer Society / ACM, (2004)Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (7): 1096-1100 (2009)Statistical Timing Analysis With Coupling., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2965-2975 (2006)Yield-Aware Cache Architectures., , , , and . MICRO, page 15-25. IEEE Computer Society, (2006)