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Power and Area Efficient VLSI Architectures for Communication Signal Processing.

, , and . ICC, page 3223-3228. IEEE, (2006)

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Addressing the Dynamic Range Problem in Cognitive Radios., , and . ICC, page 5183-5188. IEEE, (2007)An Integrated Automated Layout Generation System for DSP Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 4 (3): 285-296 (1985)A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing., , and . IEEE J. Solid State Circuits, 45 (8): 1469-1478 (2010)Millimeter-wave CMOS design., , , and . IEEE J. Solid State Circuits, 40 (1): 144-155 (2005)A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH., , and . CODES+ISSS, page 259-264. ACM, (2006)Power and Area Efficient VLSI Architectures for Communication Signal Processing., , and . ICC, page 3223-3228. IEEE, (2006)ASIC Design and Verification in an FPGA Environment., , , , , and . CICC, page 737-740. IEEE, (2007)The InfoPad Multimedia Terminal: A Portable Device for Wireless Information Access., , , and . IEEE Trans. Computers, 47 (10): 1073-1087 (1998)Processor design for portable systems., and . VLSI Signal Processing, 13 (2-3): 203-221 (1996)A perturbation theory on statistical quantization effects in fixed-point DSP with non-stationary inputs., and . ISCAS (3), page 373-376. IEEE, (2004)