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Disambiguation of "Levisse, Alexandre"

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Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters.

, , , , , and . ISVLSI, page 18-23. IEEE, (2020)

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Alexandre Martins

Alexandre Darmoise

Alexandre Varnek

Alexandre Alexeev

Alexandre Nekrassov

 

Other publications of authors with the same name

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 13 (2): 489-501 (June 2023)RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures., , , and . ASP-DAC, page 181-186. IEEE, (2020)Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology., , , , and . ACM Great Lakes Symposium on VLSI, page 513-518. ACM, (2020)Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop., , , , , , and . ISCAS, page 1-4. IEEE, (2017)Architecture, design and technology guidelines for crosspoint memories., , , , , and . NANOARCH, page 55-60. IEEE, (2017)Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations., , , , , , , , , and . IEEE Access, (2020)Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor Converters., , , , , and . ISVLSI, page 18-23. IEEE, (2020)Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems., , , and . ICASSP, page 1549-1552. IEEE, (2020)ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning., , , , , , , , and . IEEE Trans. Computers, 72 (7): 1985-1998 (July 2023)RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM., , , , , , , and . SAMOS, volume 11733 of Lecture Notes in Computer Science, page 34-47. Springer, (2019)