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Optimal Graph Constraint Reduction for Symbolic Layout Compaction., , and . DAC, page 401-406. ACM Press, (1993)Optimal clock period clustering for sequential circuits with retiming., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (6): 489-498 (1998)Continuous Retiming: Algorithms and Applications.. ICCD, page 116-121. IEEE Computer Society, (1997)Optimal Clock Period Clustering for Sequential Circuits with Retiming., , and . ICCD, page 122-127. IEEE Computer Society, (1997)FPGA Design Automation: A Survey., , and . Foundations and Trends in Electronic Design Automation, (2006)Optimal clock period FPGA technology mapping for sequential circuits., and . ACM Trans. Design Autom. Electr. Syst., 3 (3): 437-462 (1998)Desensitization for Power Reduction in Sequential Circuits., , and . DAC, page 795-800. ACM Press, (1996)Area Minimization for Hierarchical Floorplans., , and . Algorithmica, 15 (6): 550-571 (1996)FPGA HLS Today: Successes, Challenges, and Opportunities., , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 15 (4): 51:1-51:42 (2022)Identification and Preliminary SAR Analysis of Novel Type-I Inhibitors of TIE-2 via Structure-Based Virtual Screening and Biological Evaluation in in vitro Models., , , , , , , and . J. Chem. Inf. Model., 55 (12): 2693-2704 (2015)