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Register allocation for data flow graphs with conditional branches and loops., , and . EURO-DAC, page 232-237. IEEE Computer Society, (1993)A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs., , , , and . Euro-Par, Vol. I, volume 1123 of Lecture Notes in Computer Science, page 828-831. Springer, (1996)Deterministic Job Scheduling in Computing Systems.. Performance, page 241-254. North-Holland, (1976)On a Periodic Maintenance Problem., and . Oper. Res. Lett., 2 (2): 90-93 (1983)G-vector: A New Model for Glitch Analysis in Logic Circuits., , and . VLSI Signal Processing, 27 (3): 235-251 (2001)Some algebraic properties of multi-threshold functions.. IEEE Trans. Electronic Computers, 15 (6): 935-938 (1966)On a Real-Time Scheduling Problem., and . Operations Research, 26 (1): 127-140 (1978)An efficient data path synthesis algorithm for behavioral-level power optimization., , and . ISCAS (1), page 294-297. IEEE, (1999)Low Power FPGA Design - A Re-engineering Approach., , and . DAC, page 656-661. ACM Press, (1997)Crosstalk Minimization Using Wire Perturbations., and . DAC, page 100-103. ACM Press, (1999)