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A SMT-based diagnostic test generation method for combinational circuits., , , and . VTS, page 215-220. IEEE Computer Society, (2012)RTL functional test generation using factored concolic execution., and . ITC, page 1-10. IEEE, (2017)GPU-based timing-aware test generation for small delay defects., , , , , and . ETS, page 1-2. IEEE, (2014)A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms., , and . DATE, page 1427-1430. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A new hybrid solution to boost SAT solver performance., and . DATE, page 1307-1313. EDA Consortium, San Jose, CA, USA, (2007)Peak power estimation of VLSI circuits: new peak power measures., , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (4): 435-439 (2000)Set-cover-based critical implications selection to improvesat-based bounded model checking: extended abstract., , and . ACM Great Lakes Symposium on VLSI, page 331-332. ACM, (2013)Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors., , , and . J. Electron. Test., 19 (4): 437-445 (2003)Error Diagnosis of Sequential Circuits Using Region-Based Model., and . J. Electron. Test., 21 (2): 115-126 (2005)On Non-Statistical Techniques for Fast Fault Coverage Estimation.. J. Electron. Test., 15 (3): 239-254 (1999)