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Disambiguation of "Mizuno, Masayuki"

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On-Chip Optical Interconnect.

, , , , , , , , , , , , , , , , , , , , , and . Proc. IEEE, 97 (7): 1186-1198 (2009)

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Masayuki Hirosue

Jun Mizuno

Masayuki Maenishi

Masayuki Yamamoto

Masayuki Fujita

 

Other publications of authors with the same name

The numerical analysis of mass evacuation in Taipei 101 with control volume model., and . Simul. Model. Pract. Theory, (2019)A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect., , and . ISSCC, page 192-193. IEEE, (2010)Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing., , , , , , , and . ISSCC, page 470-471. IEEE, (2009)A 2.0Gb/s clock-embedded interface for full-HD 10b 120Hz LCD drivers with 1/5-rate noise-tolerant phase and frequency recovery., , , , , and . ISSCC, page 192-193. IEEE, (2009)LAGS System Using Data/Instruction Grain Power Control., , , , , , and . ISSCC, page 66-587. IEEE, (2007)A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests., , and . IEICE Trans. Electron., 94-C (1): 102-109 (2011)A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery., , , , , and . IEEE J. Solid State Circuits, 44 (12): 3560-3567 (2009)A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors., , , , , , , , and . IEEE J. Solid State Circuits, 45 (1): 15-22 (2010)An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing., , , , , , , and . IEEE J. Solid State Circuits, 45 (10): 2057-2065 (2010)A GHz MOS adaptive pipeline technique using MOS current-mode logic., , , , , , , and . IEEE J. Solid State Circuits, 31 (6): 784-791 (1996)